1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more specifically, to a semiconductor device having a structure to improve contact processing margin and a method for fabricating the same.
2. Description of the Related Art
A short interval between a contact and a non-salicide region may cause insufficient processing margin when fabricating a semiconductor device, including SRAM devices. Misalignment resulting from the insufficient processing margin at a contact forming step may cause excessive etching of a lower conductive layer. Such excessive etching of a conductive layer may adversely affect a leakage current property so that performance and/or yield of a semiconductor device may decrease.
FIG. 1 shows a portion of layout of a conventional 1T-SRAM. As shown in FIG. 1, a reference number 11 points to an active area, numbers 31 and 32 refer a first and a second conductive patterns comprising, for example, polysilicon. Number 51 refers to an insulating layer (defining a non-salicide area), and numbers 81 and 82 point to a first contact and a second contact. As shown in FIG. 1, a short interval or distance (A) between the second contact 82 and a non-salicide region 51 often causes insufficient processing margin on fabricating a semiconductor device including SRAM.
FIG. 2 shows a cross-sectional view along the II-II line of FIG. 1. As shown in FIG. 2, a first insulating pattern 21, a first conductive pattern 31 and a second conductive pattern 32 are formed on a semiconductor substrate 10. A spacer 40 is formed on a sidewall of those patterns. A second insulating pattern 51, in a non-salicide region, is over the first conductive layer 31, part of the second conductive layer 32, the spacers 40, and the exposed substrate between the spacers 40.
A first salicide 61 is on the exposed substrate in the right side of the second conductive layer 32. A second salicide 62 is also formed on the second conductive layer 32. A first contact 81 and a second contact 82 formed by etching a third insulating layer 71 are on the first salicide 61 and the second salicide 62, respectively. Here, an interval between a non-salicide region defined by the second insulating pattern 51 and the second contact 82 connected to the second salicide layer 62 on the second conductive layer 32 may be insufficient to provide a desired level of process margin. A short distance “A” between the second contact 82 and the non-salicide region 51 may cause a serious problem when misalignment happens at a contact etching step.
FIG. 3 is a sectional view showing a problem according to a conventional semiconductor device. As shown in FIG. 3, the second conductive pattern 32 in a non-salicide region may be excessively etched if misalignment happens. In the device of FIG. 3, the contact hole 82 is formed over both silicide layer 62 and insulating layer 51 defining the non-salicide region. Etching of the contact hole 82 stops on the silicide layer 62, but etches through insulating layer 51 and the underlying portion of polysilicon gate 32. As a result, it can be seen that excessive etching of a conductive layer adversely affects a leakage current property of the device so that performance and/or yield of the device drops.